Jieru Zhao (赵杰茹)

上海交通大学计算机系 副教授 博士生导师

Tenure-track Associate Professor, Ph.D. Advisor

Emerging Parallel Computing Center (EPCC)
Department of Computer Science and Engineering
Shanghai Jiao Tong University

Email: zhao-jieru@sjtu.edu.cn

Office: SEIEE Building 3-529

Short Bio
Jieru Zhao is currently a tenure-track associate professor at the Department of Computer Science and Engineering, Shanghai Jiao Tong University (SJTU). Before joining SJTU, she received the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2020, supervised by Prof. Wei Zhang , and the B.S. degree from Nanjing Univerity in 2015. She worked as a research scientist intern at DAMO academy (Aug-Nov 2020). Her research interests lie in the area of computer systems, specifically focusing on automatic design tools, hardware-software co-design and efficient AI systems. She has received two best paper awards (ICCAD'17, HPCA'24) and four best paper nominations (ISCA'24, DATE'22, SC'21, CASES'18) in top conferences.
Openings

I am looking for self-motivated PhD, Master and Undergraduate students. Please send me an email with your CV if you are interested in compiler optimization, HW-SW co-design, AI system and architecture, and machine learning for design automation.

课题组招收博士生、硕士生和对科研感兴趣的本科生，目前有如下多个科研课题：1. 大模型KV cache压缩与加速；2. 多模态模型推理加速；3. AI编译、系统、架构优化；4. AI for EDA。感兴趣的同学欢迎发邮件与我们交流。

Teaching
Professional Services
Honors and Awards
Research Group
Graduate Students Alumni Prior Undergraduate Students
Publications
  1. [DAC 2025] ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
    Guangda Liu, Chengwei Li, Jieru Zhao*, Chenqi Zhang and Minyi Guo,
    in the 62nd IEEE/ACM Design Automation Conference, 2025.
  2. [DAC 2025] StreamingGS: Voxel-Based Streaming 3D Gaussian Splatting with Memory Optimization and Architectural Support
    Chenqi Zhang, Yu Feng, Jieru Zhao*, Guangda Liu, Wenchao Ding, Chentao Wu and Minyi Guo,
    in the 62nd IEEE/ACM Design Automation Conference, 2025.
  3. [ASPLOS 2025] StreamGrid: Streaming Point Cloud Analytics via Compulsory Splitting and Deterministic Termination
    Yu Feng, Zheng Liu, Weikai Lin, Zihan Liu, Jingwen Leng, Minyi Guo, Zhezhi He, Jieru Zhao and Yuhao Zhu,
    in the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025.
  4. [HPCA 2025] RpcNIC: Enabling Efficient Datacenter RPC Offloading on PCIe-attached SmartNICs
    Jie Zhang, Hongjing Huang, Xuzheng Chen, Xiang Li, Jieru Zhao, Ming Liu, Zeke Wang,
    in IEEE International Symposium on High-Performance Computer Architecture, 2025.
  5. [ICCD 2024] AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
    Mingzhe Gao, Jieru Zhao*, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo,
    in the 42nd IEEE International Conference on Computer Design, 2024.
    Best Paper Nomination
  6. [ECCV 2024] O2V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation
    Muer Tie, Julong Wei, Zhengjun Wang, Ke Wu, Shansuai Yuan, Kaizhao Zhang, Jie Jia, Jieru Zhao, Zhongxue Gan, Wenchao Ding,
    in the European Conference on Computer Vision (ECCV) , 2024.
  7. [Preprint 2024] The CAP Principle for LLM Serving
    Pai Zeng, Zhenyu Ning, Jieru Zhao*, Weihao Cui, Mengwei Xu, Liwei Guo, Xusheng Chen, Yizhou Shan,
    Arxiv Preprint, 2024.
  8. [TCAD 2024] Automatic Mapping of Heterogeneous DNN Models on Adaptive Multi-Accelerator Systems
    Jieru Zhao*, Guan Shen, Wenchao Ding, Quan Chen, Minyi Guo,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.
  9. [ISCA 2024] A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things
    Xiaofeng Hou, Tongqiao Xu, Chao Li, Cheng Xu, Jiacheng Liu, Yang Hu, Jieru Zhao, Jingwen Leng, Kwang-Ting Cheng, Minyi Guo,
    in the 51st Annual International Symposium on Computer Architecture, 2024.
    Best Paper Nomination
  10. [TRETS 2024] FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs
    Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang,
    in ACM Transactions on Reconfigurable Technology and Systems, 2024.
  11. [HPCA 2024] An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
    Weichuang Zhang, Jieru Zhao*, Guan Shen, Quan Chen, Chen Chen, Minyi Guo,
    in the 30th IEEE International Symposium on High-Performance Computer Architecture, 2024.
    Distinguished Artifact Award
  12. [TCAD 2024] Hardware-Software Co-Design Enabling Static and Dynamic Sparse Attention Mechanisms
    Jieru Zhao*, Pai Zeng, Guan Shen, Quan Chen, Minyi Guo,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024.
  13. [ASPLOS 2024] DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflows
    Zijun Li, Chuhao Xu, Quan Chen, Jieru Zhao, Chen Chen, Minyi Guo,
    in ACM Conference on Architectural Support for Programming Languages and Operating Systems , 2024.
  14. [AAAI 2024] Swift-Mapping: Online Neural Implicit Dense Mapping in Urban Scenes
    Ke Wu, Kaizhao Zhang, Mingzhe Gao, Jieru Zhao, Zhongxue Gan, Wenchao Ding,
    in AAAI Conference on Artificial Intelligence , 2024.
  15. [DATE 2024] Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
    Mingzhe Gao, Jieru Zhao*, Zhe Lin, Minyi Guo,
    in Design, Automation and Test in Europe Conference, 2024.
  16. [TCAD 2024] AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA
    Tingyuan Liang, Gengjie Chen, Jieru Zhao*, Sharad Sinha, Wei Zhang,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.
  17. [DAC 2023] MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
    Guan Shen, Jieru Zhao*, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen and Minyi Guo,
    in the 60th Design Automation Conference, 2023.
  18. [DAC 2023] SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication
    Tao Yang, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao* and Li Jiang,
    in the 60th Design Automation Conference, 2023.
  19. [TCAD 2023] HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
    Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
  20. [ICRA 2023] FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow
    Wenchao Ding, Jieru Zhao*, Yubin Chu, Haihui Huang, Tong Qin, Chunjing Xu, Yuxiang Guan and Zhongxue Gan,
    in IEEE International Conference on Robotics and Automation , 2023.
  21. [ICS 2023] Preference-Aware Co-location Scheduling on Heterogeneous NUMA Architectures To Improve Resource Utilization
    Pu Pang, Yaoxuan Li, Bo Liu, Quan Chen, Zhou Yu, Zhibin Yu, Deze Zeng, Jingwen Leng, Jieru Zhao and Minyi Guo,
    in the ACM International Conference on Supercomputing, 2023.
  22. [HotOS 2023] Skadi: Building a Distributed Runtime for Data Systems in Disaggregated Data Centers
    Cunchen Hu, Chenxi Wang, Sa Wang, Ninghui Sun, Yungang Bao, Jieru Zhao, Sanidhya Kashyap, Pengfei Zuo, Xusheng Chen, Liangliang Xu, Qin Zhang, Hao Feng and Yizhou Shan,
    in the 19th Workshop on Hot Topics in Operating Systems, 2023.
  23. [FCS 2023] FPGA sharing in the cloud: a comprehensive analysis
    Jinyang Guo, Lu Zhang, Romero Hung José, Chao Li, Jieru Zhao, Minyi Guo,
    in Frontiers of Computer Science , 2023.
  24. [DAC 2022] SALO: an Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences
    Guan Shen, Jieru Zhao*, Quan Chen, Jingwen Leng, Chao Li and Minyi Guo,
    in the 59th Design Automation Conference , 2022.
  25. [SoCC 2022] Characterizing and Orchestrating VM Reservation in Geo-distributed Clouds to Improve the Resource Efficiency
    Jiuchen Shi, Kaihua Fu, Quan Chen, Changpeng Yang, Pengfei Huang, Mosong Zhou, Jieru Zhao, Chen Chen, Minyi Guo,
    in Symposium on Cloud Computing, 2022.
  26. [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
    Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang and Yonghong Tian,
    in IEEE Design, Automation and Test in Europe Conference and Exhibition, 2022.
    Best Paper Nomination
  27. [IPDPS 2022] CSC: Collaborative System Configuration for I/O-Intensive Applications in Multi-Tenant Clouds
    Haowei Huang, Pu Pang, Quan Chen, Jieru Zhao, Wenli Zheng, Minyi Guo,
    in International Parallel and Distributed Processing Symposium, 2022.
  28. [ICCD 2021] Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks
    Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo,
    in The 39th IEEE International Conference on Computer Design , 2021.
  29. [SC 2021] Enable Simultaneous DNN Services Based on Deterministic Operator Overlap and Precise Latency Prediction
    Weihao Cui, Han Zhao, Quan Chen, Ningxin Zheng, Jingwen Leng, Jieru Zhao, Chao Li, Minyi Guo,
    in The International Conference for High Performance Computing, Networking, Storage, and Analysis, 2021.
    Best Reproducibility Advancement Award Finalist
  30. [ICCAD 2021] AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
    Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang,
    in IEEE/ACM International Conference on Computer-Aided Design, 2021.
  31. [FPL 2020] FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
    Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang and Shaojie Shen,
    in IEEE International Conference on Field Programmable Logic and Applications, 2020. (long oral presentation, acceptance rate: 24/158=15.2%)
    [Paper] [Code]
  32. [ASP-DAC 2020] HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
    Zhe Lin, Jieru Zhao, Sharad Sinha and Wei Zhang,
    in IEEE Asia and South Pacific Design Automation Conference, 2020. (acceptance rate: 86/250=34.4%)
    [Paper] [Slides]
  33. [TCAD 2020] Performance Modeling and Directives Optimization for High-level Synthesis on FPGA
    Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang and Bingsheng He,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
    [Paper] [Code]
  34. [DAC 2019] LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms
    Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in ACM/IEEE Design Automation Conference, 2019. (acceptance rate: 202/1068 = 18.9%)
    [Paper]
  35. [ICCAD 2019] Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
    Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha and Wei Zhang,
    in IEEE/ACM International Conference on Computer-Aided Design, 2019. (acceptance rate: 94/394 = 23.9%)
    [Paper] [Code]
  36. [DATE 2019] Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
    Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in IEEE Design, Automation and Test in Europe Conference and Exhibition , 2019. (long oral presentation, acceptance rate: 202/834 = 24.2%)
    [Paper] [Slides]
  37. [FPGA 2019] A Hybrid Data-Consistent Framework for Link-Aware Access Management in Emerging CPU-FPGA Platforms
    Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
    [Poster]
  38. [TCAD & CASES 2018] Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
    Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha and Wei Zhang,
    in IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, 2018. (journal-track, acceptance rate: 69/270 = 25.5%)
    Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.
    Best Paper Nomination
    [Paper] [Slides] [Code]
  39. [ICCAD 2017] COMBA: A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
    Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang and Bingsheng He,
    in IEEE/ACM International Conference on Computer-Aided Design, 2017. (acceptance rate: 105/399 = 26.3%)
    Best Paper Award
    [Paper] [Slides] [Code]
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Last updated on March, 2024 by Jieru.