Jieru Zhao (赵杰茹)

上海交通大学计算机系 助理教授 博士生导师

Tenure-track Assistant Professor, Ph.D. Advisor

Emerging Parallel Computing Center (EPCC)
Department of Computer Science and Engineering
Shanghai Jiao Tong University

Email: zhao-jieru AT sjtu DOT edu DOT cn

Office: SEIEE Building 3-529


Short Bio
Jieru Zhao joined the Department of Computer Science and Engineering, Shanghai Jiao Tong University (SJTU) as an Assistant Professor in December, 2020. Prior to that, she received the Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology in 2020, and the B.S. degree from Nanjing Univerity in 2015. She worked as a research scientist intern at DAMO academy (Aug-Nov 2020). Her research interests lie in the area of computer systems, specifically focusing on automatic design tools, hardware-software co-design and energy-efficient computing systems. Her current research projects aim at improving the programmability of customizable computing for software engineers from cloud to edge devices.

Openings

I am looking for self-motivated PhD, Master and Undergraduate students. Please send me an email with your CV if you are interested in compiler optimization, HW-SW co-design, computer systems, computer architecture, and machine learning for EDA.

本团队正在招募博士生、硕士生和对科学研究感兴趣的本科生,如果你对AI编译、软硬件协同设计、FPGA加速、高层次综合、计算机系统、计算机体系结构等感兴趣,欢迎发邮件与我联系。

目前正在招收2022级博士生和硕士生,欢迎计算机/电子/微电子及相关专业的同学与我联系。
Teaching

Professional Services

Honors and Awards

Research Group

Publications
  1. [ICCD 2021] Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks
    Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo,
    in The 39th IEEE International Conference on Computer Design , 2021. To appear.
  2. [SC 2021] Enable Simultaneous DNN Services Based on Deterministic Operator Overlap and Precise Latency Prediction
    Weihao Cui, Han Zhao, Quan Chen, Ningxin Zheng, Jingwen Leng, Jieru Zhao, Chao Li, Minyi Guo,
    in The International Conference for High Performance Computing, Networking, Storage, and Analysis, 2021. To appear.
  3. [ICCAD 2021] AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
    Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang,
    in IEEE/ACM International Conference on Computer-Aided Design, 2021. To appear.
  4. [FPL 2020] FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
    Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang and Shaojie Shen,
    in IEEE International Conference on Field Programmable Logic and Applications, 2020. (long oral presentation, acceptance rate: 24/158=15.2%)
    [Paper] [Code]
  5. [ASP-DAC 2020] HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
    Zhe Lin, Jieru Zhao, Sharad Sinha and Wei Zhang,
    in IEEE Asia and South Pacific Design Automation Conference, 2020. (acceptance rate: 86/250=34.4%)
    [Paper] [Slides]
  6. [TCAD 2019] Performance Modeling and Directives Optimization for High-level Synthesis on FPGA
    Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang and Bingsheng He,
    in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
    [Paper] [Code]
  7. [DAC 2019] LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms
    Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in ACM/IEEE Design Automation Conference, 2019. (acceptance rate: 202/1068 = 18.9%)
    [Paper]
  8. [ICCAD 2019] Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
    Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha and Wei Zhang,
    in IEEE/ACM International Conference on Computer-Aided Design, 2019. (acceptance rate: 94/394 = 23.9%)
    [Paper] [Code]
  9. [DATE 2019] Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
    Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in IEEE Design, Automation and Test in Europe Conference and Exhibition , 2019. (long oral presentation, acceptance rate: 202/834 = 24.2%)
    [Paper] [Slides]
  10. [FPGA 2019] A Hybrid Data-Consistent Framework for Link-Aware Access Management in Emerging CPU-FPGA Platforms
    Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha and Wei Zhang,
    in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
    [Poster]
  11. [TCAD & CASES 2018] Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
    Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha and Wei Zhang,
    in IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, 2018. (journal-track, acceptance rate: 69/270 = 25.5%)
    Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.
    Best Paper Nomination
    [Paper] [Slides] [Code]
  12. [ICCAD 2017] COMBA: A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
    Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang and Bingsheng He,
    in IEEE/ACM International Conference on Computer-Aided Design, 2017. (acceptance rate: 105/399 = 26.3%)
    Best Paper Award
    [Paper] [Slides] [Code]